3-bit Multiplier Verilog Code Apr 2026

full_adder fa3 ( .a(s2), .b(pp2[1]), .cin(c3), .sum(s3), .cout(c5) );

half_adder ha2 ( .a(pp2[0]), .b(1'b0), .sum(s2), .carry(c3) );

// Helper modules module half_adder ( input a, b, output sum, carry ); assign sum = a ^ b; assign carry = a & b; endmodule 3-bit multiplier verilog code

// Instantiate behavioral multiplier (change as needed) multiplier_3bit_behavioral uut ( .a(a), .b(b), .product(product) );

initial begin $monitor("a=%d (%b) b=%d (%b) product=%d (%b)", a, a, b, b, product, product); for (int i = 0; i < 8; i++) begin for (int j = 0; j < 8; j++) begin a = i; b = j; #10; end end $finish; end endmodule a=0 (000) b=0 (000) product=0 (000000) a=1 (001) b=2 (010) product=2 (000010) a=3 (011) b=3 (011) product=9 (001001) a=5 (101) b=6 (110) product=30 (011110) a=7 (111) b=7 (111) product=49 (110001) Key Points | Feature | Behavioral | Structural | |---------|-----------|-------------| | Code size | Small | Large | | Readability | High | Low | | Synthesis | Good (modern tools) | Explicit control | | Area/speed | Tool-optimized | Manual tuning | full_adder fa3 (

// Stage 3 full_adder fa2 ( .a(s1), .b(pp1[2]), .cin(c2), .sum(product[2]), .cout(c4) );

for most FPGA/ASIC designs unless you need explicit gate-level control for teaching or low-level optimization. full_adder fa3 ( .a(s2)

// Stage 2 full_adder fa1 ( .a(pp0[2]), .b(pp1[1]), .cin(c1), .sum(s1), .cout(c2) );

// Full adder chain // Stage 1: pp0[1] + pp1[0] half_adder ha1 ( .a(pp0[1]), .b(pp1[0]), .sum(product[1]), .carry(c1) );